1. Field of the Invention
The present invention relates to a buck converter, and more particularly, to a buck converter capable of direct current (DC) offset cancellation and internal ripple compensation.
2. Description of the Prior Art
With advanced development in technology, various electronic products, such as a notebook, a mobile phone, a personal digital assistant, a multimedia player, etc., have been presented and are utilized widely in daily life. In general, a power converter is required for providing operating power for the electronic products. Furthermore, the power converter is capable of converting a high voltage AC power or DC power to a low voltage and stable DC power for operation of the electronic products. The buck power converter is one type of power converter, which can offer advantages of simplicity, low cost, and high efficiency. Therefore, the buck power converter has widely been applied in various electronic products.
Please refer to FIG. 1, which is a schematic diagram of a buck converter 10 with constant on time control scheme according to the prior art. The buck converter 10 is utilized for converting an input voltage VI into a stable output voltage VO for a load Load. The buck converter 10 includes a comparator 102, a constant-on-time trigger 104, a pre-driver 106, a high side switch HS, a low side switch LS, an output inductor LO, an equivalent series resistor ESR, and an output capacitor CO. The interconnections of the units of the buck converter 10 are as shown in FIG. 1 and further description is omitted for brevity. The comparator 102 generates a comparison result CMP, which is outputted to the constant-on-time trigger 104, according to a reference voltage VREF and a feedback voltage VFB. The constant-on-time trigger 104 generates a trigger control signal STON having a fixed on-time period TON, which is outputted to the pre-driver 106. The pre-driver 106 generates a first pre-driving signal UG and a second pre-driving signal LG to control an on/off state of the high side switch HS and the low side switch LS according to the trigger control signal STON. For example, during an on-time period TON, the high switch HS is switched into an on state and the low switch LS is switched into an off state. Similarly, during an off-time period TOFF, the high switch HS is switched into an off state and the low switch LS is switched into an on state. Furthermore, when the on-time period TON is a fixed value, the length of the off-time period TOFF depends on level of the feedback voltage VFB. In other words, the off-time period TOFF is modulated for output voltage regulation by a negative feedback mechanism. For example, during the off-time period TOFF, as the output voltage VO (i.e. the feedback voltage VFB) is lower than the reference voltage VREF, the next switching cycle period is triggered (i.e. the next on-time period TON begins). However, when the equivalent series resistor ESR is too small, the ripple voltage generated by the equivalent series resistor ESR may become too small. As a result, a sub-harmonic oscillation occurs, thus, the buck converter 10 becomes unstable. Please refer to FIG. 2, which is a schematic diagram of signal waveforms of the buck converter 10 shown in FIG. 1 when the buck converter 10 powers a heavy load and the equivalent series resistor ESR is 0.05 milliohms. As shown in FIG. 2, when the buck converter 10 transitions from a light load state (at the period T1) into a heavy load state (at the period T2), i.e. the inductor current ILO of the output inductor LO changes from 1 ampere to 5 amperes, each voltage signal becomes unstable after the period T1, thus the whole system becomes unstable. A multi-layer ceramic capacitor (MLCC) is often applied as the output capacitor CO in high frequency and portable electronic products. However, the equivalent series resistance of the MLCC is relatively small. In the buck converter 10, sufficient equivalent series resistance of the output capacitor CO is required for generating a suitable ripple voltage for preserving the stable constant on time scheme.
Please refer to FIG. 3, which is a schematic diagram of a buck converter 30 for reducing sub-harmonic oscillation according to the prior art. In the buck converter 30, a substitution resistor Rj placed in the feedback loop replaces the function of the equivalent series resistor ESR shown in FIG. 1, and the stability of the buck converter 30 can be improved by adjusting the substitution resistor Rj. As shown in FIG. 3, a summation voltage signal of the sum of a compensation voltage Vsen and a reference voltage VREF can be provided to the comparator 102. In such a situation, an extra ripple voltage is added to the feedback loop to enhance the output voltage VO for improving the sub-harmonic oscillation effect. Also, because the substitution resistor Rj is an internal circuit of a chip, the substitution resistor Rj can be controlled to provide a proper resistance for realizing system stability.
Moreover, please further refer to FIG. 1. The prior art can provide an extra ripple voltage for the buck converter 100 by transforming the current sensed from the output inductor LO to the corresponding voltage and accordingly adding the corresponding voltage to the positive input terminal and/or the negative input terminal of the comparator 102 for improving system stability. Otherwise, in the prior art, the sensed inductor current can be AC-coupled to the positive input terminal and/or the negative input terminal of the comparator 102 for providing an extra ripple voltage for the buck converter 100. However, though adding the extra ripple voltage to the comparator 102 may improve the low ripple voltage problem (resulting from low equivalent series resistor ESR), but the above-mentioned extra ripple voltage added to the feedback loop usually has an extra DC component so that a voltage offset effect may occur on the output voltage VO. For example, please refer to FIG. 4, which is a schematic diagram of signal waveforms of the buck converter 10 shown in FIG. 1 when a load transient occurs. The buck converter 10 is in light load state during the periods T1 and T3, and in heavy load state during the period T2. As can been seen, the voltage offset effect is larger when the load is heavier. For example, in an area A in FIG. 4, it is obvious that a large voltage offset effect occurs during the load transient. In short, the prior art may improve the low ripple voltage problem, but the voltage offset effect of the output voltage still reduces system performance.